Dynamic range improvements of load modulated amplifiers

ABSTRACT

The present invention relates to methods and devices to control and operate the functionality of a power amplifier system ( 100 ) capable of operating in at least three differential amplification modes. The drive signal&#39;s amplitude envelope controls an integrated switch network ( 104; 105, 106 ) that routes both the signal envelope and signal phase to different modulation blocks ( 111, 112: 109, 110: 115 ). Depending on the envelope strength, the operational mode of the amplifier system is possible to alter to best serve the signal statistics to provide the highest overall power efficiency.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to power amplifiers andamplifying methods, and more specifically to high efficiency poweramplifiers.

DESCRIPTION OF RELATED ART

In radio transmitters for broadcast, cellular and satellite systems thepower amplifier in the transmitter has to be very linear in addition tobeing able to simultaneously amplify many radio channels (i.e.frequencies) spread across a wide bandwidth. High linearity is requiredsince nonlinear amplifiers would cause leakage of interfering signalenergy between channels and distortion within each channel.

In the wireless communication industry, a premium is placed on theability to amplify wide bandwidth signals. e.g. spread spectrum signals,in highly efficient manner. To limit the size of the DC power supply andcooling equipment in a radio base station, it is essential to keep ahigh overall power efficiency. Various attempts have been made toaddress this problem, however it remains difficult to design a highefficiency power amplifier system that is at the same time also able tolinearly amplify wide bandwidth signals.

One such system is the Feed forward amplification system, in which theoutput signal from the amplifier stage is compared to the input signalto be able to determine the difference-signal. To outbalance thenon-desired distortion components due to non-linear amplification, saiddifference-signal is amplified to a suitable amount and added inreversed phase to the output signal from the power amplifier.

In a pre-distortion amplifier system however, the input signal firstpasses a non-linear pre-distorter, which is an inverse non-linearfunction to the transfer function of the power stage. Thus, thepre-distortion of the input signal will automatically compensate for thedistortion generated by the power stage. In an adaptive pre-distortionsystem, correction values are stored in a look-up table arrangement ofwhich the output is due to the incoming vector amplitude and the outputsignals amplitude and phase.

Another known method and system for power amplifying is EER (EnvelopeElimination and Restoration). The method is to determine the envelope ofthe input signal and regenerate it on the output by means of amodulating step. The amplifier operates with constant gain and outputamplitude.

Further, another known system and method is called Envelope Tracking. Bythis, the output signal is compared to the input drive signal forgenerating an amplifier control signal. Said signal controls the gain ofthe system and compensates for deviations. The system comprises at leasttwo amplifier stages, which are operating according to a linearfunction.

Doherty is another method for power amplifying a drive signal. A Dohertysystem comprises a linear class A amplifier and a non-linear, highefficiency amplifier, e.g. a class C amplifier. The peak power isreceived by the non-linear amplifier.

Polar loop and Cartesian loop are two other known methods and systemsused in power output stages.

The Polar loop system involves separate control of amplitude and phase.The actual value of the amplitude of the drive signal and the desiredvalue are compared in a differential stage that is capable of modulatingthe RF output signal. In a Phase-Locked Loop (PLL) comprising a VCO(Voltage-Controlled Oscillator) and phase detector the actual value ofthe phase of the drive signal and the desired value compared and is usedfor controlling the phase.

The Cartesian loop system comprises a Cartesian loop. This system isoperated with the rectangular component I and Q vectors (In-phase andQuadrature-phase). The system is a feedback system wherein the outputsignal is separated in the I and Q output vectors, which are compared tothe input I and Q vectors, respectively.

Another system, which is promising for the future, is theSigma-Delta-modulation system for modulation of a class E amplifier or aclass F amplifier.

In radio transmitter stations for cellular systems, amplifiers in classA and B are commonly used in combination with LINC (LINC, LinearAmplification using Nonlinear Components) or Chireix outphasing methodsproviding high linearity and efficiency, and wide bandwidth.

The outphasing method, resolves an envelope-modulated bandpass waveformof the drive signal in a signal component separator into two out-phasedconstant envelope signals s₁ and s₂, which are applied to poweramplifiers. The outputs of the power amplifiers are combined in a hybridarrangement recovering the envelope-modulated waveform. The outputamplitude of the amplified output signal is a result of the phase shiftbetween the signals s₁ and s₂. When the signals are in phase, amplitudemaximum is achieved and when in anti-phase, a minimum amplitude isachieved. The hybrid combiner is designed for the two constant envelopesignals to combine distortion-less into the original signal at animpedance level that is matched to receive maximum output power. Onlythe coherent parts of the two signals of constant envelope are combinedat the output of the hybrid. The efficiency ratio will be reciprocallyproportional to the ratio between peak power and mean power. Byreplacing the impedance load by a compensating reactance network, knownas the Chireix method, the region of high efficiency is extended toinclude lower output power levels.

LINC and Chireix networks are sensitive systems that fits well withunbalanced amplifier like class A and B amplifiers.

It is also known in prior art to combine different amplificationtechniques. From the U.S. patent publication 2005/0280466 A1 anamplification system comprising a combination of Chireix and Dohertytechniques is already known. Doherty is used in the upper power dynamic,referred to as the Load Modulation Region. In the region below loadmodulation region, outphasing with Chireix network is used forincreasing the efficiency in said lower region. Both in Doherty andChireix, the amplifiers are utilized as voltage generators. In the knownsystem, said amplifiers are combined by an impedance inverter. When theDoherty amplifiers are active, the main transistor of said configurationwill be influenced by an impedance increase and, therefore, theavailable power will decrease. In the Chireix case, both amplifiers areinfluenced by the impedance increase as the phase difference between thetwo branches increases reducing the available power while the deliveredpower decreases due to outphasing. In both Doherty and Chireix, theefficiency is maintained. In one embodiment of the known system, theoutput voltage to block 330, i.e. Doherty block, is controlled accordingto the described EER method.

The known Chireix/Doherty combination has a number of drawbacks. Signalcombining networks are not trivial to implement and it is especiallycomplicated to attain the desired operation of the amplifier system whenutilizing Chireix networks. Further, the efficiency of Chireix issensitive for parasitic disturbances and decreases rapidly due toparasitic components in the transistors of the system.

A common problem for the above listed systems and methods is theirlimited capability to linearly amplify wide bandwidth signals. Further,it is desirable to avoid said drawbacks of the signal combining networkand facilitate implementation.

SUMMARY

An object of the present invention is to address above stated problem tolinearly amplify wide bandwidth signals and at the same time with a highpower efficiency.

One idea according to the present invention is to control and operatethe functionality of a power amplifier system capable of operating in atleast three differential amplification modes. The drive signal envelopecontrols an integrated switch network that routes both the signalenvelope and signal phase to two different modulation blocks.

One idea of the architecture of the present invention is basically to beable to use amplifiers in at least three different modes wherever thepower efficiency might be strongest. Depending on the envelope strength,the operational mode of the amplifier system is possible to alter tobest serve the signal statistics to provide the highest overall powerefficiency.

The above described problems may be solved according to the presentinvented method for power amplifying an input drive signal to a poweramplification system comprising at least three different poweramplification modes, wherein each amplification mode is dedicated tooperate within a pre-determined amplification interval. The method iscomprising the step of determining the momentary envelope value of theinput drive signal, and the step of switching amplification mode to oneof the at least three amplification modes depending on the determinedmomentary envelope value.

Further, the above described problems may be solved by means of thepresent invented amplifier system for power amplifying an input drivesignal to the system, which system is arranged to operate in at leastthree different power amplification modes. Each amplification mode isdedicated to operate within a pre-determined amplification interval. Thepresent system comprises:

-   -   determining device for determining the momentary envelope value        of the input drive signal; and    -   switching amplification mode device for switching to one of the        at least three amplification modes depending on the determined        momentary envelope value received from the determining means.

The present invention may be included in a radio base station in amobile radio telecommunication network, wherein said base stationcomprises an amplifier system according to the invention and thedifferent embodiments.

The described problems are solved by means of an invented switchingamplification mode device in a power amplifying system for poweramplifying an input drive signal to the system. The system is arrangedto operate in at least three different power amplification modes,wherein each amplification mode is dedicated to operate within apre-determined amplification interval. Said system is comprising adetermining device for determining the momentary envelope value of theinput drive signal, wherein the switching amplification mode device isarranged to switch the system to operate in one of the at least threeamplification modes depending on the momentary envelope value receivedfrom the determining device.

Different embodiments of the invented method, amplifier system, radiobase station and switching amplification mode device are described inthe detailed description hereafter.

This is a technique suitable for amplifiers that work poorly when theinput signal is backed off like the Current mode Class D, Class B, ClassC, Class D, Class E, Class E/F and Class F amplifiers. For example byusing load modulation in combination with outphasing and EER, theefficiency can be maintained over the output power range where theimpedance tuner can track the optimum impedance for the amplifier ateach power level. Outside the tunable area the efficiency drops quicklybut the dynamic range of the system is increased so that highly dynamicsignals like the UMTS signals still can be amplified linearly into theload.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will in the following be described in more detail withreference to enclosed drawings, wherein:

FIG. 1 a is a possible variation over time of an input signal, drivesignal, S_(in)(t) to a power amplification system according to thepresent invention illustrated.

FIG. 1 b is the envelope signal E corresponding to the input signal,drive signal, S_(in)(t) illustrated in FIG. 1 a.

FIG. 2 is a flowchart diagram illustrating the method according to thepresent invention;

FIG. 3 shows a block diagram of a preferred embodiment of a poweramplifier system according to present invention:

FIG. 4 shows a block diagram illustrating when the power amplifiersystem in FIG. 2 is operated in outphasing mode;

FIG. 5 shows a block diagram illustrating when the power amplifiersystem in FIG. 2 is operated in EER mode;

FIG. 6 shows a block diagram illustrating when the power amplifiersystem in FIG. 2 is operated in Dynamic Load (DL) modulation mode;

FIG. 7 is a block diagram illustrating a base station configurationcomprising the amplifier system according to the invention;

FIG. 8 is a block diagram showing a dynamic load modulation device;

FIG. 9 is a block diagram schematically illustrating a complex phasemodulator for use in the present invention.

FIG. 10A is a block diagram illustrating a mode switching device of thepresent invention when the power amplifier system is operating inoutphasing mode;

FIG. 10B is a block diagram illustrating a mode switching device of thepresent invention when the power amplifier system is operating in EERmode;

FIG. 10C is a block diagram illustrating a mode switching device of thepresent invention when the power amplifier system is operating in DLmode;

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein: rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

In FIG. 1 a is a possible variation over time of an input signal, drivesignal, S_(in)(t) to a power amplification system according to thepresent invention illustrated. One idea according to the presentinvention is to control the functionality of a power amplifier systemcapable of operating in at least three different amplification modes.For this purpose, an envelope signal is determined. The envelope E ofthe drive signal controls an integrated switch network that routes boththe signal envelope and signal phase to two different modulation blocks.If the power amplifier system is to be operated in three differentamplification modes, two different pre-determined threshold values TH1and TH2, where TH2>TH1, are used. The envelope signal and said thresholdvalues are illustrated in FIG. 1 b. As an example, when the signalenvelope E is larger than some pre-determined threshold, i.e. envelopevalue E is larger than threshold TH2, the operation is set to DynamicLoad (modulation) mode. If the signal envelope E is determined to bebetween the two thresholds, i.e. TH1<E<TH2, the operation is set to EERmode. Finally, if the envelope E is measured to be lower than TH1, i.e.0<E<TH1, outphasing mode is set as operation mode of the amplifiersystem. Thus, three mode operation intervals may be defined: the firstmode operation interval, e.g. [0, TH1) (i.e. 0<E<TH1) where the systemis defined to operate in the first amplification mode if E is equal toTH1, the second amplification mode interval, e.g. [TH1,TH2[ (i.e.TH1<E≦TH2) where the system is defined to operate in the firstamplification mode if E is equal to TH1 and in the second mode if E isequal to TH2, and finally the third amplification mode interval if E isgreater than TH2. e.g. ]TH2, ∞[ (i.e. TH2<E<∞). It is obvious to aperson skilled in the art that it is necessary to decide whether asystem should operate in the first or second mode if E is equal to TH1,or in the second or third mode if E equals TH2. However, such a decisionis open for any choice of mode and one choice is not better thananother. The system will operate equally well.

More generally, the method according to the present invention isillustrated in a flowchart of FIG. 2. The method is illustrated as anendless loop, wherein the different steps are performed depending on theenvelope measure value and the threshold values that is preset beforestart. Threshold value TH1 is set to be less than threshold value TH2.

In the first step, Step 1, the momentary value of the envelope iscontinuously determined, by means (102 in FIG. 3) for determining themomentary envelope value, hereafter denoted E or amplitude value E, ofthe drive signal fed to the power amplifier system. The amplitude valueE is a function of the drive signal. In the next step, Step 2, thedetermined amplitude E is compared in a means (104 in FIG. 3) forswitching amplification mode. Said means may have a control input forreceiving an amplitude value indication, an analogue signal or a digitalvalue indicating the momentary amplitude E. Said value E is compared tothe lowest of the preset threshold values, TH1. If the condition E<TH1is true, indicated as “yes” in FIG. 2, the amplifier system is set tooperate in the first mode. The system will remain in this mode, orstate, as long as E does not exceeds TH1. However, when E exceeds TH1,the condition is not true any longer, indicated as “no” in FIG. 1, andthe device for switching mode will switch to either of the two otheramplification modes, the second or the third, depending on whether E isexceeding TH2 or not. Therefore, in Step 4, E is compared to TH2. If Edoesn't exceed TH2, the amplifier system is controlled and set tooperate in the second mode, Step 5, and the system will remain there aslong as the comparison condition in step 4 is not true (NO), or Edecreases to a value less than TH1, or if E increases to a valueexceeding TH2. If E decreases to a measure less than TH1, the systemwill switch to operate in the first mode, but if E increases to a valuehigher than TH2, the comparison condition E>TH2 is true (yes), theamplifier system is controlled and set to operate in the third mode,Step 5, and the system will remain there as long as the comparisoncondition in Step 4 is true. When the condition of Step 4 is not trueany longer, the system amplification mode will be switched to either thefirst mode due to the fact that E<TH1 in Step 2, or to the second modedue to the fact that E does not exceed TH2 in Step 4, but exceeds TH1 inStep 2.

Regardless which amplification mode that the amplifier system is set tooperate, the method loop will be continuously run through causing acontinuous determination and measurement of the drive signal envelope inStep 1 and mode switch will only be performed when E is determined toswitch amplification mode interval.

In the following described preferred embodiment, the three differentmodes are the outphasing mode, the Envelope Elimination and Restoration(EER) mode and the Dynamic Load modulation (DL) mode.

A preferred embodiment of the amplifier system 100 according to thepresent invention will now be presented with reference to FIG. 3. Theamplifier system is illustrated as a radio architecture for use in aradio base transmitter of a mobile radio telecommunication network. Aninput drive signal S_(in) to be amplified may according to already knownmethods be transformed into I- and Q-vector pairs in a basebandgenerator 101. Further, said I- and Q-vector pair are converted intopolar coordinates representing the resulting amplitude and phase of thevector sum of said pair by the IQ-to-Amplitude/phase converter block102, which is a well-known process to a person skilled in the art. Saidresulting amplitude, i.e. the envelope signal E(t) and phase θ isseparately fed to a digital pre-distortion block, DPD block 103.

Said DPD block 103 is used for linearization of the power amplifiers ifnecessary, and therefore optional. It is more and more common that thelinearization is performed in the digital domain. Instead of usingRF-components, or even in some cases low frequency analogue componentsto accomplish pre-distortion, one is more inclined to make use ofrapidly emerging high-speed signal processors such as Digital SignalProcessors, DSP, and Field Programmable Gate Array, FPGA, which can befurther integrated into an ASIC. It not only lets you implement morecomplex DPD solutions, it also turns up to be a cost-saver for theoverall radio implementation. It can be implemented as a look-up table(LUT) with the envelope of the signal at base band as the only entryindex. The signal at base band will then be multiplied by this tableoutput using both amplitude and phase. Memory effects can be taken careof by a similar method only requiring one or several similar instancesof the LUT architecture in parallel.

The DPD functional block 103 may be placed either before theIQ-to-Amplitude/phase conversion, or optionally after it. In eithercase, the pre-distortion will be a function of the envelope only,modifying the amplitude of the signal, or possibly also the phasecomponent of it. Digital Pre-Distortion is a well-known technique fromearlier published documentation, e.g. the international publishedapplication No. WO2004/086607 A1, and the U.S. Pat. No. 6,545,535. Bymeans of what is known from above mentioned documents, a person skilledin the art will be able to design a DPD functional block 103.

To be able to switch between the different amplification modes, theoutphasing mode, the Envelope Elimination and Restoration (EER) mode andthe Dynamic Load (DL) modulation mode, an amplification mode switchingblock 104 is introduced in the amplifier system according to theinvention.

The mode switching device 104, constituting the switching means forswitching amplification mode, is in this embodiment divided into twoseparate switching blocks, but it is possible to be implemented andregarded as one block only or several separated blocks. According to theillustrated embodiment, the mode switching block 104 is separated intoan EER/Dynamic Load mode Switching block (EDLS) 105 and a Phasemodulation/Outphasing mode Switching block (POS) 106, respectively. Animplementation of the switching block(-s) will be discussed in moredetail with reference to FIGS. 10A-10C, which are schematic blockdiagrams showing an implementation EDLS 105 and POS 106 of the modeswitching block 104 in the three different modes.

The EER/Dynamic Load mode Switching block (EDLS) 105 receives themomentary amplitude value generated by the IQ-to-Amplitude/phaseconversion block 102 and DPD block 103 arrangement irrespectively of theindividual order of said two blocks. The EDLS 105 is designed to forwardthe actual amplitude value E in EER mode and DL mode, respectively, butblocks said amplitude value E and forward a predetermined control value,e.g. unit value, in Outphasing mode. The EDLS 105 has one input 105A twooutput ports 105B and 105C, wherein the first output port 105B is activeduring the DL mode and the second output port 105C is active during theEER mode. During the Outphasing mode, both outputs are active forwardingsaid control value, e.g. unit value, which facilitates the amplifiersystem to be operated in said mode.

The Phase modulation/Outphasing mode Switching block (POS) 106 has fourinput ports 106A-106D and two output ports 106E-106F.

An implementation of the switching block(-s) is illustrated in FIGS.10A-10C, which are schematic block diagrams showing an implementation ofthe EDLS 105 and POS 106 of the mode switching block 104 (see FIG. 3) inthe three different modes, respectively, according to the inventedmethod as described in FIG. 2.

The momentary amplitude value generated by the IQ-to-Amplitude/phaseconversion block and DPD block arrangement 102-103 irrespective of theindividual order of said two blocks is received on the first input port106A of the POS 106. Thus, both the POS and the EDLS are connected tothe output port 103A of the IQ-to-Amplitude/phase conversion block andDPD block arrangement. The second input port 103B is connected to theoutput of a complex phase modulator 107, which will be described in moredetail in connection to FIG. 9. The complex phase modulator 107generates a complex phase modulation signal θ, corresponding to a phasedifference for a desired power amplification level of the PAs 111 and112, said signal is transferred both to the first output port 106E andthe second output port 106F of the POS when the amplifier system isoperated in EER mode and DL mode. For achieving operation in theOutphasing mode, the third 106E and fourth input 106F of the POS 106 areconnected to a Outphasing split block 108, which design is regarded asknown to a person skilled in the art by prior art documentation. TheOutphasing principle generally means a method for obtaining amplitudemodulation by combining two phase modulated constant amplitude voltagesproduced by a signal component separating means. In this embodiment, theoutphasing split block generates the two constant amplitude signals andwhich phase difference is a measure of the input amplitude. When the twosignals are in phase, a maximal output signal is generated, but aminimal amplitude is generated if the two signal is in counter phase.The two signals from the split block will be separately transferred tothe first output and second output, respectively.

As the outputs from EDLS are a digital signal and the devices 109-112 isanalogue operating circuits, digital-to-analogue converters DAC 156, 157is needed for performing the conversion.

The upper switching block, EDLS 105, selects whether the envelope is tobe sent to the dynamic load modulation devices 109 and 110, i.e. in DLmode operation, or to be sent to control the gate directly of the poweramplifiers 111 and 112 according to EER mode operation. The lowerswitching block, POS 106, controls if the two outphasing signals inoutphasing operation mode shall be sent to the two power amplifiers 111and 112, or if the phase modulated RF-signal should be sent in equalproportions to the power amplifiers 111, 112 of the amplifier system.

The first output port 106E of the POS 106 is connected to a first poweramplifier branch 113, and the second output port 106F is connected to asecond power amplifier (PA) branch 114. Each PA branch 113 comprises apower amplifier and a dynamic load device and in the radio architecturedesign an IQ-modulator step. The output of each PA branch is connectedto an adder device 115 that generates an output signal equal to orcorresponding to the sum of said PA output signals.

The two branches 113 and 114 are configured and designed in the sameway. Therefore, by describing the design and function of one PA branch,both PA branches are regarded as described in detail.

The first output 106E of the POS 106 is connected to the IQ-modulatorstep of the first PA branch. The IQ-modulator step comprises anIQ-compensator 151, a digital-to-analogue converter 152 and anIQ-modulator 153. Optionally, a limiter may be included directly afterand connected to the IQ-modulator. The function of said limiter is toform a square wave on the output as a function of the input signal.Thereby, it will be possible to feed the power amplifier system withsquare waves.

The IQ-compensator 153 is a complex-valued up-converter design. Thisimplementation involves a simple complex-valued multiplication betweenthe base band IQ-representation with a complex-valued oscillator signaltuned at carrier frequency. As the RF-signal is real, only the realcomponent of the signal is presented to the PA.

As the radio architecture according to state-of-the art is of the formdirect up-conversion from complex base band to RF, the IQ-modulator 153is of analogue form. As such it will suffer from RF impairments and hasto be corrected for by an IQ-compensator 151. The IQ-compensatorcorrects for irregularities at base band such as IQ-leakage and DCleakage. The leakage consists of a cross-coupling effects in thecircuits between the I-component and the Q-component of the complexsignal. In addition there might be a DC (Direct current) leakage. Theseleakage quantities have to be calibrated fairly accurately in order tokeep the adjacent channel at a low level. The compensation can readilybe made at digital base band. However, this IQ-compensation will not bediscussed in more detail as it is regarded as not essential forunderstanding the present invention. By means of a local oscillator 154,it will be possible to control and generate the transmit radiofrequency.

The RF-modulated signal is connected to the power amplifier PA of the PAbranch. The power amplified signal is connected to a dynamic load device109. The dynamic load device 109 may be implemented as a controllableimpedance tuner or filter. The amplitude control signal, also referredto as the envelope control signal, to the tuner is received from one ofthe output of the EDLS 105. The dynamic load device 109 is only used inthe DL mode for amplitude modulation of the output RF-signal from the PA111, and is designed to have as little effect as possible duringoperation in the other two modes. As stated before, the output of thedynamic load device 109, which is the final step of the PA branch, isconnected to one of the inputs of the adder device 115. The output ofthe second parallel PA branch 114 is also connected to the adder 115,and the output signal S_(OUT) is the vector sum of the two outputsignals received from the first and second PA branches.

The design of the adder device 115 may be an isolated hybrid combiner ora Wilkinson combiner. It is important that the adder device isolates thetwo branches 113 and 114, respectively, from each other. If the twobranches are isolated, the branches will not influence each other andtheir performance. According to the Chireix method, said branches arenot separated from each other. The isolated hybrid combiner or aWilkinson combiner are well-known to a person skilled in the art ofelectronic circuit design and the design will therefore not be discussedin more detail.

The architecture of the present invention comprises a pair of amplifiersoperated in all three different modes depending on when the powerefficiency might be strongest. Depending on the envelope strength, theoperational mode of the amplifier system is possible to alter to bestserve the signal statistics to provide the highest overall powerefficiency. For this purpose two different pre-determined thresholdvalues TH1 and TH2, where TH2>TH1, are used.

In a best mode of the invention, when the signal envelope E is largerthan some pre-determined threshold, i.e. envelope value E is larger thanthreshold TH2, the operation is set to Dynamic Load (modulation) mode.If the signal envelope E is determined to be between the two thresholds,i.e. TH1<abs(E)<TH1, the operation is set to EER mode. Finally, if theenvelope E is measured to be lower than TH1, i.e. abs(E)<TH1, outphasingmode is set as operation mode of the amplifier system.

In another embodiment of the invention, when the signal envelope E islarger than some pre-determined threshold, i.e. envelope value E islarger than threshold TH2, the operation is set to EER mode. If thesignal envelope E is determined to be between the two thresholds. i.e.TH1<abs(E)<TH1, the operation is set to Dynamic Load (modulation) mode.Outphasing mode is set as operation mode of the amplifier system whenthe envelope E is measured to be lower than TH1, i.e. abs(E)<TH1.

However, the invention provides the possibility to use more thresholdvalues than two. The invention also provides possibility to operate theamplification system in more than three modes. In such other modes, thesystem is operated according to a combination of at least two of thestated amplification techniques outphasing, DL or EER. As an example, DLand EER may be used simultaneously in a combination mode.

For the sake of clarity, it must be particularly expressed that thepower amplifier system according to the invention is described whenincorporated in a radio architecture. In the radio architecture, theIQ-modulator 153 including the Local Oscillator (LO) device 154 and theIQ-compensator 151 including devices 155 is added to the power amplifiersystem according to the invention. Thus, in the basic invented poweramplifier system 100 said devices 151, 153, 154 and 155 is excluded.

The operation of a best mode of the amplifier system in each of thethree modes will now be discussed and presented in more detail withreference to FIGS. 4, 5 and 6.

In FIG. 4, the above presented radio architecture of the power amplifiersystem 100 according to the invention of FIG. 3 is operated inoutphasing mode, i.e. outphasing technique is used.

The outphasing method is well-known and earlier described, e.g. in thepatent application publication No. US 2005/0248401 A1, in the patentdocument No. U.S. Pat. No. 6,825,719 B1, in the patent document U.S.Pat. No. 7,030,714 B2, and in the article “RF power amplifiers forWireless Communications”, by Steve C. Cripps, pp. 240-246, Artech HousePublishers, April 1999, ISBN 0890069891. A more detailed description ofthe outphasing method and architecture seems therefore not necessary.

When the amplification mode switching block 104 receives an amplitudevalue E within an amplification mode interval wherein outphasingtechnique is set to be used, said block 104 will connect the twonecessary constant envelope signals S₁ and S₂ provided by the outphasingsplit block 108, one of the signals to the first PA branch 113 and theother signal to the second PA branch 114.

The object of the Outphasing split block 108 is to present two constantenvelope signals so that when added together they reconstruct theoriginal signal with time varying amplitude and phase. The basebandsignal, defined as S_(in)(t)=Re{I+jQ}, is split into an amplitudecomponent and a phase difference part by the IQ-to-Amplitude/phaseconversion block 102. The block 108 has one input for said amplitudecomponent and one input for said phase difference part. The constantenvelope signals and the two amplifiers 111, 112 ensures that a fullylinear amplification of the RF signal is achieved. It is astraightforward matter in the digital domain to split the signalsuitable for the outphasing modulated amplifiers 111, 112.

The complex versions of the signals S₁(t) and S₂(t) are:

S ₁(t)=Re{e ^(jωt) ·e ^(jφ) ·e ^(j cos) ⁻¹ ^(E)} and S ₂(t)=Re{e ^(jwt)·e ^(jφ) ·e ^(−j cos) ⁻¹ ^(E)}

It is readily seen that S₁(t) and S₂(t) are two signals of constantenvelope E, phase difference φ, and carrier frequency ω. Now, by simplealgebraic manipulations we can extract the amplitude part out of theparenthesis to get it appear as a real quantity in front of the complexsignal, in the following manner:

S ₁(t)+S ₂(t)=2·E·Re{e ^(jωt) ·e ^(jφ)}

As can be easily understood, by extracting the real part of the complexexpression above a real expression for an RF-modulated signal havingboth amplitude and phase variations. An example of such a signal is theWCDMA-signal which is modelled at complex base band by simultaneousamplitude and phase signal. If the output signal from the adder isdefined as Y(t), and the gain of both power amplifiers is G, the outputS_(OUT) is:

S _(OUT)(t)=2·G·E·cos(ωt+φ)

The EER (Envelope Elimination and Restoration) method is also well-knownand earlier described, e.g. in the patent application publication No. US2002/0008574 A1, see especially sections [0004]-[0005] and sections[0023]-[0029], and the article “RF power amplifiers for WirelessCommunications”, by Steve C. Cripps, pp. 246-247, Artech HousePublishers, April 1999, ISBN 0890069891. A more detailed description ofthe EER method and architecture seems therefore not necessary.

In FIG. 5, a preferred embodiment of the invention is illustrated whenoperated in EER mode.

When the amplification mode switching block 104 receives an amplitudevalue E within an amplification mode interval wherein EER technique isset to be used, said block 104 will block the two constant envelopesignals S₁ and S₂ provided by the outphasing split block 108.

However, the baseband signal, defined as S_(in)(t)=Re{I+jQ}, is in thesame way as in the outphasing method split into an amplitude componentand a phase difference part by the IQ-to-Amplitude/phase conversionblock 102. The amplitude component is forwarded by the EDLS 105 andcontrols the bias of the power amplifiers 111, 112 in the two amplifierbranches 113, 114. When the amplifier system 100 is operated in EERmode, the complex phase modulator 107 generates from said phasedifference part a complex phase modulation signal that is transferred tothe first and second output port of the POS 106 and further introducedin each power amplifier branch 113,114. If the output signal from theadder 115 is defined as S_(OUT)(t), and the gain of both poweramplifiers is G(E(t)), the output S_(OUT) may be described as:

S _(OUT)(t)=2·G(E(t))·Ph(t)=A(t)·Re{e ^(j(ωt+φ)) }=A′ cos(ωt+φ),

wherein A′ is equal to the amplified amplitude modulation coefficient,E(t) is the amplitude component and Ph(t) is the phase component. Thecomplex phase modulator's contribution is identified as e^(jφ) and thecomplex up-converter's contribution as e^(jωt). Thus, the signal Ph(t)is generated and provided by the complex phase modulator and the complexup-converter.

The DL (Dynamic Load) method is also well-known and earlier described.e.g. in the article “High-Efficiency Linear Amplification by DynamicLoad Modulation” by Frederick H. Raab, 2003 IEEE Met-S Digest, pp.1717-1720.

In FIG. 6, a preferred embodiment of the invention is illustrated whenoperated in DL mode. As in the EER-mode, the output signals of theoutphasing splitter device is blocked by the mode switching block 104.The baseband signal, defined as S_(in)(t)=Re{I+jQ}, is in the same wayas in the other two above described methods split into an amplitudecomponent and a phase difference part by the IQ-to-Amplitude/phaseconversion block 102. The amplitude component is forwarded by the EDLS105 via the first output 105A, but controls the bias of the dynamic loaddevices 109, 110 in the two amplifier branches 113, 114. As when theamplifier system is operated in EER mode, the complex phase modulator107 generates from said phase difference part a complex phase modulationsignal that is transferred to the first 106E and second output port 106Fof the POS 106 and further introduced in each power amplifier branch113, 114. If the output signal from the adder is defined as S_(OUT)(t),and the gain of each power amplifiers is G, the output S_(OUT)(t) may bedescribed as:

S _(OUT)(t)=2·E(t)·G·Ph(t)=A·Re{e ^(j(ωt+φ)) }=A′ cos(ωt+φ),

wherein A′ is equal to the amplified amplitude modulation coefficient,E(t) is the amplitude component and Ph(t) is the phase component.

In the above described embodiment, two different threshold values andthree different amplification techniques are used. However, it shall beunderstood that the present invention is not limited to said number andset of threshold values and amplification techniques. Additionalthreshold values and/or other amplification techniques may be as wellintroduced within the scope of the claimed invention.

The present invention is preferably adapted for use in radio terminals,e.g. mobile radio terminals or base stations of cellular mobile radiotelecommunications systems, or within satellite systems.

FIG. 7 is a schematic illustration of a WCDMA network architecture 600comprising base stations 620, node B. The network comprises a Corenetwork 605 to which a number of Radio Network Controllers 610 (RNC) areconnected and other networks 608, e.g. Public Switched Telephony Network(PSTN), Public data Networks. Internet, Integrated Services DigitalNetwork (ISDSN), other Public Land Mobile Networks (PLMN), Satellitetelecommunication systems, etc. The RNC 610 controls at least onededicated node B 620 (Base Station in GSM networks). The RNC 620controls and handles the uplink and downlink communications over the airinterface between a node B 620 (connected to the RNC) and subscriberunits, such as radio handset terminals 630. A node B comprises, amongother units (not shown), Base Band units 622, Radio Units 624, FilterUnits 626 and an antenna system 628. The Base Band unit 622 transformsdigital messages into I and Q vectors, which are transferred to theRadio Unit 624. In the Radio Unit, said vectors are modulated oncarriers resulting in signals S_(in). Before transmission, the signalsS_(in) are power amplified. Therefore, the Radio Unit is equipped withat least one composite power amplifier system 200 according to theinvention. The amplifier system 200 power amplifies s_(in) and providesan output signal S_(OUT) to the antenna system 628 for transmission overa radio channel to a subscriber unit 630. e.g. a radio terminal handset.

It is also possible to use the composite power amplifier system 200according to the invention in a satellite 650 for mobile radiotelecommunications or in mobile radio terminal, also denoted handset,for mobile radio telecommunications. The satellite will then operate asa repeater station comprising transmitters and/or transceivers in theRadio Units 624 and antenna systems 628 for handling the communicationwith a control station in a Satellite telecommunication systems 608 andsatellite radio terminals 630 located on the earth.

An embodiment of a dynamic load device 109, 110 implemented as alossless impedance tuner 430 is presented in FIG. 8, which is a circuitdiagram. The use and control of impedance tuners are earlier known to aperson skilled in the art, for example from the document“High-Efficiency Linear Amplification by Dynamic Load Modulation” byFrederick H. Raab, pp. 1717-1720, 2003 IEEE MIT-S Digest. The presentimpedance tuner 430 is a tunable filter arrangement, which comprises atransmission line 435 with a constant impedance Z₀ and an diodearrangement 431. The diode arrangement comprises two diodes 432 and 433,here varactor diodes, which cathodes are connected, as illustrated inthe figure. Both diodes are charged in the reverse direction, the firstdiode by a DC bias source 434 and the second diode by earth potential.Their cathodes are connected to an input for a control voltage v_(cntrl)that will be able to control the diode capacitance of the diodes. Bycontrolling the diode capacitances, it is possible to adjust theimpedance to compensate for the reactance effect depending on thecurrent power level and achieve a pure optimal resistive load at eachpower level. In this embodiment, the input control voltage v_(cntrl) isreceived from the first output 105B of the EDLS 105.

In FIG. 9, a complex phase modulator 107 is illustrated. The momentaryphase difference φ generated by the IQ-to-Amplitude/phase conversionblock and DPD block arrangement 102-103, irrespective of the individualorder of said two blocks, is received on the second input port 106B ofthe POS 106. The second input port 103B is connected to the output of acomplex phase modulator 107, which complex phase modulator 107generates, from the inserted phase difference φ, a complex phasemodulation signal e^(jφ)=cos φ+j sin φ that is transferred both to thefirst output port 106E and the second output port 106F of the POS 106when the amplifier system is operated in EER mode and DL mode. The phasedifference signal cp is split and fed to a cosine signal generator 450Aand sine signal generator 450B, respectively. The cosine signal and sinesignal is fed in parallel to a Complex converter block 460, which outputcomplex phase modulation signal e^(jφ) is transferred to the secondinput port 106B of the POS 106.

An implementation of the switching block(-s) is illustrated in FIGS.10A-10C, which are schematic block diagrams showing an implementation ofthe EDLS 105 and POS 106 of the mode switching block 104 (see FIG. 2) inthe three different modes, respectively, according to the inventedmethod as described in FIG. 2.

The upper switching block, EDLS 105, selects whether the envelope is tobe sent to the dynamic load modulation means 109 and 110, i.e. DL modeoperation, or to be sent to control the gate directly of the poweramplifiers 111 and 112 according to EER mode operation. The lowerswitching block, POS 106, controls if the two outphasing signals inoutphasing operation mode shall be sent to the two power amplifiers 111and 112, or if the phase modulated RF-signal should be sent in equalproportions to the power amplifiers 111, 112 of the amplifier system.

The EER/Dynamic Load mode Switching block (EDLS) 105 has one input 105A,and two output ports 105B and 105C. As described in the description inconnection with FIG. 2, the EDLS 105 receives on input 105A themomentary amplitude value E generated by the IQ-to-Amplitude/phaseconversion block 102 and DPD block 103 arrangement irrespective of theindividual order of said two blocks. The EDLS comprises switchingdevices 202, 204, and 206, each one having a voltage control port 205.The control port 205 of this first switching device 202 is connectedinput 105A. The switching device 202 will switch between the two inputs202A and 202B depending on if the envelope value E exceeds thresholdvalue TH1 or not. Input 202A is connected to input port 105A, and inputport 202B is connected to a unit amplitude voltage supply 212. Theoutput 202C is connected to the control port 205 of the two secondswitching device 204 and 206, respectively, wherein switching device 204is connected to output port 105B and switching device 206 is connectedto output port 105C. The switching device 204 and 206 will switchbetween inputs 204A or 204B, and 206A or 206B, respectively, dependingon if the envelope value E exceeds threshold value TH2 or not.

In the illustrated embodiment, the first input port 204A of switchingdevice 204 and second input port 206B of switching device 206 areconnected to the output port 202C of the first switching device 202. Thesecond input port 204B of switching device 204 and first input port 206Aof switching device 206 are connected to the unit amplitude voltagesupply 212. Depending on if E exceeds TH2 or not, the two secondswitching device 204, 206 will switch simultaneously and forward theactual amplitude value E on the first output port 105B in DL mode whenE>TH2, as illustrated in FIG. 10C and FIG. 6, and on the second outputport 105C in EER mode when E<TH2, as illustrated in FIG. 10B and FIG. 5,but blocks said amplitude value E and forward a predetermined controlvalue on both output ports 105B,105C in Outphasing mode as illustratedin FIG. 10A and FIG. 4.

However, in another embodiment of the invention that is not illustrated,but easily understood, the two second switching device 204, 206 mayswitch simultaneously and forward the actual amplitude value E on thesecond output port 105C and allow the amplifier system to operate in DLmode when E<TH2, and on the first output port 105B allow the amplifiersystem to operate in EER mode when E>TH2. Output port 105C is in thisembodiment connected to the dynamic load device 109, 110, and Outputport 105B is connected to the amplifier pairs 111, 112.

The Phase modulation/Outphasing mode Switching block (POS) 106 has fourinput ports 106A-106D and two output ports 106E-106F. As illustrated inFIG. 2, the momentary amplitude value generated by theIQ-to-Amplitude/phase conversion block and DPD block arrangement 102-103irrespective of the individual order of said two blocks is received onthe first input port 106A of the POS 106. Thus, both the POS and theEDLS are connected to the output port 103A of the IQ-to-Amplitude/phaseconversion block and DPD block arrangement. The second input port 106Bis connected to the output of a complex phase modulator 107, whichgenerates a complex phase modulation signal that is transferred both tothe first output port 106E and the second output port 106F of the POSwhen the amplifier system is operated in EER mode and DL mode. Forachieving operation in the Outphasing mode, the third 106C and fourthinput 106D of the POS 106 are connected to a Outphasing split block 108.

The first output port 106E of the POS 106 is connected to a first poweramplifier branch 113, and the second output port 106F is connected to asecond power amplifier (PA) branch 114.

The POS 106 comprises a first switching device 208 and a secondswitching device 210. The control voltage ports 205 of said switchingdevice are both connected to input port 106A of the POS 106. The firstswitching device 208 will switch between the two inputs 208A and 208Bdepending on if the envelope value E exceeds threshold value TH1 or not.The second switching device 210 will simultaneously switch between thetwo inputs 210A and 210B depending on if the envelope value E exceedsthreshold value TH1 or not. Both the first input 208A of switchingdevice 208 and the first input 210A of the second switching device 210is connected to the second input port of the POS 106. The second input208B of the first switching device 208 is connected to the third input106C of the POS 106 and the second input 210B of the second switchingdevice 208 is connected to the fourth input 106D of the POS 106.

In the Outphasing mode, when E is less (or equals) TH1, the first output106E is connected to the third input 106C and second output 106F of thePOS 106 is connected to the fourth input 106D as illustrated in FIG. 10Aand FIG. 4. When E exceeds threshold TH1, the switching devicesimultaneously switches, and the complex phase modulation signal istransferred both to the first output port 106E and the second outputport 106F of the POS when the amplifier system is operated in EER mode,see FIG. 10B and FIG. 5, and DL mode, see FIG. 10C and FIG. 6,respectively.

It is possible to adjust and pre-set the threshold values TH1 and TH2 ofthe switching device to any wished value.

In the description of the invented system, a number of control signals,or control values, are handled by the mode switching block 105. Thevalue E(t) is used as input signal on input 105A of the EDSL 105 of themode switching block 104. The relation to the input signal S(t) may bedefined as E(t)=abs(S(t))=A(t), if the input signal S(t) is a complexbaseband signal defined as S(t)=A(t)*e^(iφ(t)), wherein A(t) is thesignal amplitude, A(t)>0. If the system gain is G, the output signal ofthe system is S_(out)(t)=G*S(t).

The EDSL 105 is also capable of generating two control signals, V_(DL)on output 105B and V_(EER) on output 105C. V_(DL) is the control valuefor the load tuners 109, 110 and it corresponds to a vector lengthabs(S_(out)). V_(EER) is the control value for the PAs 111, 112 and italso corresponds to a vector length abs(S_(out)).

The phase difference θ between the phase signals on the inputs 106C and106D will vary between θ_(min)=180 and θ_(max)=0 depending on thecomplex baseband input signal S(t). θ_(min) is the phase difference thatcorresponds to a minimum abs(S_(out)). θ_(max) is the phase differencethat corresponds to a maximum abs(S_(out)).

The control signals are digital signals and are therefore converted bythe DACs 156 and 157, respectively.

TH1 is set to level N1 and TH2 is set to level N2, where N1, N2>0 andN2>N1. The two levels are defining the three amplificationintervals—first, second and third amplification intervals. The firstinterval is defined as 0≦E(t)≦N1 (or 0≦E(t)<N1), the secondamplification interval is defined as N1<E(t)≦N2 (or N1≦E(t)≦N2 orN1<E(t)<N2 or N1≦E(t)<N2) and the third amplification interval E(t)>N2(or E(t)≧N2).

The values V_(DL), V_(EER), and θ of said control signals when E(t) isvarying (the column to the left) is shown in Table 1.

TABLE 1 E(t) V_(DL) V_(EER) θ 0 1 1 180 . 1 1 . . 1 1 . . 1 1 . N1 E(t)1 0 . E(t) 1 0 . E(t) 1 0 . E(t) 1 0 N2 1 E(t) 0 . 1 E(t) 0 . 1 E(t) 0

Therefore, in the first amplification interval, i.e. 0≦E(t)≦N1 (or0≦E(t)<N1), when the outphasing technique is used, the phase differenceθ between the phase signals on the inputs 106C and 106D will varybetween θ_(min) and θ_(max), and V_(DL) on output 105B is set to a unitvalue “1” and V_(EER) on output 105C is also unit value “1”.

In the second amplification interval, i.e. N1<E(t)≦N2 (or N1≦E(t)≦N2 orN1<E(t)<N2 or N1≦E(t)<N2), when the EER amplification is used, the phasedifference θ is set to θ_(max), and V_(DL) on output 105B is varyingwith or depending on E(t) and V_(EER) on output 105C is set to the unitvalue “1”.

In the third amplification interval, i.e. E(t)>N2 (or E(t)≧N2), when theDL amplification is used, the phase difference θ is still θ_(max)(=0),and V_(DL) on output 105B is set to the unit value “1”, V_(EER) onoutput 105C is varying with or depending on E(t).

Another possible implementation (not shown) of the switching block(-s),i.e. the mode switching block 104 or the EDLS 105 and POS 106, is to usea Look-up-Table arrangement comprising storage means storingpredetermined control values corresponding to current envelope values.

As stated above in the description, the invention provides thepossibility to use more threshold values than two. The invention alsoprovides possibility to operate the amplification system in more thanthree modes. In such other modes, the system is operated according to acombination of at least two of the stated amplification techniquesoutphasing, DL or EER.

The present invention may be embodied in many different forms and shouldnot be construed as limited to the embodiments set forth herein: rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the invention asdefined by the enclosed set of claims.

1. A method for power amplifying an input drive signal to a poweramplification system comprising at least three different poweramplification modes, wherein each amplification mode is dedicated tooperate within a pre-determined amplification interval, said methodcomprising the step of determining the momentary envelope value (E) ofthe input drive signal (S_(in)) (step 1), and the step of: switchingamplification mode to one of the at least three amplification modesdepending on the determined momentary envelope value (E).
 2. The methodaccording to claim 1, wherein the switching step comprises the steps of:operating the power amplification system in a first amplification modeif the momentary envelope value (E) is determined to be within a firstamplification interval (steps 2 and 3); operating the poweramplification system in a second amplification mode if the momentaryenvelope value (E) is determined to be within a second amplificationinterval (steps 4 and 5); operating the power amplification system in athird amplification mode if the momentary envelope value (E) isdetermined to be within a third amplification interval (steps 4 and 6).3. The method according to claim 2, wherein when the system is operatedin the first amplification mode, an outphasing technique is used forpower amplifying the input drive signal.
 4. The method according toclaim 3, wherein when the system is operated in the second amplificationmode, a Dynamic Load modulation technique is used for power amplifyingthe input drive signal.
 5. The method according to claim 3, wherein whenthe system is operated in the second amplification mode, an EnvelopeElimination and Restoration (EER) technique is used for power amplifyingthe input drive signal.
 6. The method according to claim 4, wherein whenthe system is operated in the third amplification mode, an EnvelopeElimination and Restoration (EER) technique is used for power amplifyingthe input drive signal.
 7. The method according to claim 5, wherein whenthe system is operated in the third amplification mode, a Dynamic Loadtechnique is used for power amplifying the input drive signal.
 8. Themethod according to any of the preceding claims, wherein the poweramplification system comprises a pair of amplifiers.
 9. The methodaccording to claim 8, wherein the amplifiers may be any of amplifierclass B, C, D, E, E/F, F.
 10. A power amplifying system (100) for poweramplifying an input drive signal (S_(in)) to the system, which system isarranged to operate in at least three different power amplificationmodes, wherein each amplification mode is dedicated to operate within apre-determined amplification interval, and which system comprises:determining device (102, 103) for determining the momentary envelopevalue (E) of the input drive signal; and switching amplification modedevice (104; 105,106) for switching to one of the at least threeamplification modes depending on the determined momentary envelope value(E) received from the determining device (102, 103).
 11. The systemaccording to claim 10, wherein the switching amplification mode devicecomprises: switching device (104) switching the power amplificationsystem to a first amplification mode if the momentary envelope value (E)is determined to be within a first amplification interval, or switchingthe power amplification system to a second amplification mode if themomentary envelope value (E) is determined to be within a secondamplification interval, or switching the power amplification system to athird amplification mode if the momentary envelope value (E) isdetermined to be within a third amplification interval.
 12. The systemaccording to claim 11, wherein if the system is operated in the firstamplification mode, an outphasing technique is used for power amplifyingthe input drive signal.
 13. The system according to claim 12, wherein ifthe system is operated in the second amplification mode, a Dynamic Loadmodulation technique is used for power amplifying the input drivesignal.
 14. The system according to claim 13, wherein if the system isoperated in the third amplification mode, an Envelope Elimination andRestoration (EER) technique is used for power amplifying the input drivesignal.
 15. The system according to claim 12, wherein if the system isoperated in the second amplification mode, an Envelope Elimination andRestoration (EER) technique is used for power amplifying the input drivesignal.
 16. The system according to claim 15, wherein if the system isoperated in the third amplification mode, a Dynamic Load technique isused for power amplifying the input drive signal.
 17. The systemaccording to any of the preceding claims, wherein the poweramplification system comprises a pair of amplifiers.
 18. The systemaccording to claim 17, wherein the amplifiers may be any of amplifierclass B, C, D, E. E/F, F
 19. A radio base station in a mobile radiotelecommunication network, wherein said base station comprises anamplifier system according to any of claims 10-18.
 20. A switchingamplification mode device (104;105,106) in a power amplifying system(100) for power amplifying an input drive signal (S_(in)) to the system,which system is arranged to operate in at least three different poweramplification modes, wherein each amplification mode is dedicated tooperate within a pre-determined amplification interval, said system(100) comprising determining device (102, 103) for determining themomentary envelope value (E) of the input drive signal, wherein theswitching amplification mode device (104;105,106) is arranged to switchthe system to operate in one of the at least three amplification modesdepending on the momentary envelope value (E) received from thedetermining device (102, 103).
 21. The switching amplification modedevice according to claim 20, wherein the switching device (104) isarranged to switching the power amplification system to a firstamplification mode if the momentary envelope value (E) is determined tobe within a first amplification interval, or switching the poweramplification system to a second amplification mode if the momentaryenvelope value (E) is determined to be within a second amplificationinterval, or switching the power amplification system to a thirdamplification mode if the momentary envelope value (E) is determined tobe within a third amplification interval.
 22. The switchingamplification mode device according to claim 21, wherein if the systemis operated in the first amplification mode, an outphasing technique isused for power amplifying the input drive signal.
 23. The switchingamplification mode device according to claim 22, wherein if the systemis operated in the second amplification mode, a Dynamic Load modulationtechnique is used for power amplifying the input drive signal.
 24. Theswitching amplification mode device according to claim 23, wherein ifthe system is operated in the third amplification mode, an EnvelopeElimination and Restoration (EER) technique is used for power amplifyingthe input drive signal.
 25. The switching amplification mode deviceaccording to claim 22, wherein if the system is operated in the secondamplification mode, an Envelope Elimination and Restoration (EER)technique is used for power amplifying the input drive signal.
 26. Theswitching amplification mode device according to claim 25, wherein ifthe system is operated in the third amplification mode, a Dynamic Loadtechnique is used for power amplifying the input drive signal.
 27. Theswitching amplification mode device according to any of the precedingclaims, wherein the power amplification system comprises a pair ofamplifiers.
 28. The switching amplification mode device according toclaim 27, wherein the amplifiers may be any of amplifier class B, C, D,E, E/F, F.